description the A3995 is designed to drive two dc motors at currents up to 2.4 a. capable of drive voltages up to 36 v, the A3995 includes two independent fixed off-time pwm current regulators that operate in either fast or slow decay mode, as determined by the mode input. internal synchronous rectification control circuitry is provided to improve power dissipation during pwm operation. protection features include: thermal shutdown with hysteresis, undervoltage lockout (uvlo) and crossover current protection. special power-up sequencing is not required. the A3995 is supplied in a 36 pin qfn package (suffix ev) with exposed power tab for enhanced thermal performance. it has a 6 mm 6 mm footprint, with a nominal overall package height of 0.90 mm, and is lead (pb) free, with 100% matte tin leadframe plating. A3995ds features and benefits ? 36 v output rating ? 2.4 a dc motor driver ? synchronous rectification ? internal undervoltage lockout (uvlo) ? thermal shutdown circuitry ? crossover-current protection ? very thin profile qfn package dmos dual full bridge pwm motor driver package: 36 pin qfn 0.90 mm nominal height (suffix ev) A3995 approximate scale 1:1 typical application diagram microcontroller or controller logic mode1 phase1 enable1 vref1 mode2 phase2 enable2 vref2 vdd cp1 cp2 vcp vbb vbb out1a out1b sense1 out1b out1a sense1 out2a out2b sense2 out2b out2a sense2 gnd gnd A3995 gnd gnd
dmos dual full bridge pwm motor driver A3995 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb -0.5 to 36 v pulsed t w < 1 s 38 v logic supply voltage v dd C0.4 to 7 v output current * i out continuous .4 a pulsed t w < 1s 3.5 a logic input voltage range v in C0.3 to 7 v sensex pin voltage v sensex 0.5 v pulsed t w < 1s .5 v vref x pin voltage v refx .5 v operating temperature range t a range s C0 to 85 oc junction temperature t j (max) 150 oc storage temperature range t stg C55 to 150 oc * may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. thermal characteristics (may require derating at maximum conditions) 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 25 50 75 100 125 150 175 temperature (c) power dissipation, p d (mw) power dissipation versus ambient temperature (r q ja = 27 oc/w) ev package 4-layer pcb selection guide part number packing A3995sev-t 61 pieces per tube A3995sevtr-t 1500 pieces per reel characteristic symbol test conditions min. units package thermal resistance r ja ev package, 4 layer pcb based on jedec standard 7 oc/w
dmos dual full bridge pwm motor driver A3995 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com c h a r g e p u m p d m o s full bridge 1 d m o s full bridge 2 v c p m o d e 1 p h a s e 1 e n a b l e 1 o u t 1 b o u t 1 a s e n s e 2 o u t 2 b o u t 2 a v c p o s c s e n s e 2 v r e f 2 c o n t r o l l o g i c g a t e d r i v e v c p + - + - s e n s e 1 s e n s e 2 p w m l a t c h b l a n k i n g p w m l a t c h b l a n k i n g 3 c o n t r o l l o g i c g a t e d r i v e g n d g n d c p 1 v b b c p 1 3 v r e f 1 m o d e 2 p h a s e 2 e n a b l e 2 v b b v d d o u t 1 a o u t 1 b o u t 2 a o u t 2 b s e n s e 2 s e n s e 1 s e n s e 1 g n d g n d n c n c n c n c n c n c r s 2 r s 1 functional block diagram
dmos dual full bridge pwm motor driver A3995 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics 1 , valid at t a = 25 c, v bb = 36 v, unless otherwise noted characteristics symbol test conditions min. typ. max. units load supply voltage range v bb operating 8.0 C 36 v logic supply voltage range v dd operating 3.0 C 5.5 v vdd supply current i dd C 7 10 ma output on resistance r ds(on) source driver, i out = C1. a, t j = 5c C 350 450 m sink driver, i out = 1. a, t j = 5c C 350 450 m v f , outputs i out = 1. a C C 1. v output leakage i dss outputs, v out = 0 to v bb C0 C 0 a vbb supply current i bb i out = 0 ma, outputs on, pwm = 50 khz, dc = 50% C C 8 ma control logic logic input voltage v in(1) 0.7v dd C C v v in(0) C C 0.3v dd v logic input current i in v in = 0 to 5 v C0 <1.0 0 a input hysteresis v hys 150 300 500 mv propagation delay times t pd pwm change to source on 350 550 1000 ns pwm change to source off 35 C 300 ns pwm change to sink on 350 550 1000 ns pwm change to sink off 35 C 50 ns crossover delay t cod 300 45 1000 ns blank time t blank .5 3. 4 s vref x pin input voltage range v ref x operating 0.0 C 1.5 v vref x pin reference input current i ref v ref = 1.5 C C 1 a protection circuits vbb uvlo threshold v uv(vbb) v bb rising 7.3 7.6 7.9 v vbb hysteresis v uv(vbb)hys 400 500 600 mv vdd uvlo threshold v uv(vdd) v dd rising .65 .8 .95 v vdd hysteresis v uv(vdd)hys 75 105 15 mv thermal shutdown temperature t jtsd 155 165 175 c thermal shutdown hysteresis t jtsdhys C 15 C c 1 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for indi - vidual units, within the specified maximum and minimum limits. 3 v err = [(v ref /3) C v sense ] / (v ref /3). dc control logic phase enable mode outa outb function 1 1 1 h l forward (slow decay sr) 1 1 0 h l forward (fast decay sr) 0 1 1 l h reverse (slow decay sr) 0 1 0 l h reverse (fast decay sr) x 0 1 l l brake (slow decay sr) 1 0 0 l h fast decay sr* 0 0 0 h l fast decay sr* * to prevent reversal of current during fast decay sr C the outputs will go to the high impedance state as the current gets near zero.
dmos dual full bridge pwm motor driver A3995 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com e n b p h m o d e o u t a o u t b i o u t v b b v b b 1 2 3 4 1 v b b 0 v v b b 0 v 2 3 4 5 6 7 6 7 8 9 9 8 a a c h a r g e p u m p a n d v r e g p o w e r -u p d e l a y ( z 2 0 0 s) o u t b o u t a o u t a o u t b 5 0 a logic timing diagram, dc driver
dmos dual full bridge pwm motor driver A3995 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com device operation the A3995 is designed to operate two dc motors. the currents in each of the output full-bridges, all n-channel dmos, are regulated with fixed off-time pulse width modulated (pwm) control circuitry. the peak current to each full bridge is set by the value of an external current sense resistor, r sx , and a reference voltage, v refx . if the logic inputs are pulled up to vdd, it is good practice to use a high value pullup resistor in order to limit current to the logic inputs should an overvoltage event occur. logic inputs include: phasex, enablex, and mode. internal pwm current control each full-bridge is con - trolled by a fixed off-time pwm current control circuit that limits the load current to a desired value, i trip . initially, a diagonal pair of source and sink dmos outputs are enabled and current flows through the motor winding and r sx . when the voltage across the current sense resistor equals the voltage on the vrefx pin, the current sense comparator resets the pwm latch, which turns off the source driver. the maximum value of current limiting is set by the selection of r s and the voltage at the vref input with a transconductance function approximated by: i tripmax = v ref / (3r s ) note: it is critical to ensure that the maximum rating of 500 mv on each sensex pin is not exceeded. fixed off-time the internal pwm current control circuitry uses a one shot circuit to control the time the drivers remain off. the one shot off-time, t off , is internally set to 30 s. blanking this function blanks the output of the current sense comparator when the outputs are switched by the internal current control circuitry. the comparator output is blanked to prevent false detections of overcurrent conditions, due to reverse recovery currents of the clamp diodes, or to switching transients related to the capacitance of the load. the driver blank time, t blank , is approximately 3 s. phase input (phasex) the state of the phasex input determines the direction of rotation of the motor. control logic dc motor commutation is accomplished by applying a pwm signal together with the phase or enable inputs. fast or slow current decay during the off-time is selected via the mode pin. synchronous rectification is always active regardless of the state of the mode pin. charge pump (cp1 and cp2) the charge pump is used to generate a gate supply greater than the v bb in order to drive the source-side dmos gates. a 0.1 f ceramic capacitor should be connected between cp1 and cp2 for pumping purposes. a 0.1 f ceramic capacitor is required between vcp and vbbx to act as a reservoir to operate the high-side dmos devices. shutdown in the event of a fault (excessive junction tem - perature, or low voltage on vcp), the outputs of the device are disabled until the fault condition is removed. at power-up, the undervoltage lockout (uvlo) circuit disables the drivers. synchronous rectification when a pwm-off cycle is triggered by an internal fixed off-time cycle, load current will recirculate. the A3995 synchronous rectification feature will turn on the appropriate mosfets during the current decay. this effectively shorts the body diode with the low r ds(on) driver. this significantly lowers power dissipation. when a zero current level is detected, synchronous rectification is turned off to prevent reversal of the load current. mode control input mode is used to toggle between fast decay mode and slow decay mode. a logic high puts the device in slow decay mode. synchronous rectification is always enabled when enable is low. braking the braking function is implemented by driving the device in slow decay mode via the mode pin and applying an enable chop command. because it is possible to drive current in both directions through the dmos switches, this configura - tion effectively shorts the motor-generated bemf as long as the enable chop mode is asserted. the maximum current can be approximated by v bemf /r l . care should be taken to ensure that the maximum ratings of the device are not exceeded in worst case braking situations: high speed and high inertia loads. functional description functional description
dmos dual full bridge pwm motor driver A3995 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com u1 cin1 cvdd1 vdd out1b gnd gnd gnd cin3 vbb out1a cvdd2 rs2 rs1 cvcp cin2 ccp out2a out2b figure 5. printed circuit board layout with typical application circuit, shown at right. the copper area directly under the A3995 (u1) is soldered to the exposed thermal pad on the underside of the device. the thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the pcb , so the two copper areas together form the star ground. ev package layout shown. motor configurations for applications that require either a stepper/dc motor driver or dual stepper motor driver, allegro offers the a3989 and a3988. these devices are offered in the same qfn package as the A3995. the a3988 is capable of driving 2 bipolar stepper motors at output currents up to 1.2 a. the stepper control logic is industry standard parallel communication. please refer to the allegro website for further information and datasheets about those devices. layout the printed circuit board should use a heavy ground - plane. for optimum electrical and thermal performance, the A3995 must be soldered directly onto the board. on the under - side of the A3995 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad should be soldered directly to an exposed surface on the pcb. thermal vias are used to transfer heat to other layers of the pcb. grounding in order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single- point ground, known as a star ground , located very close to the device. by making the connection between the exposed thermal pad and the groundplane directly under the A3995, that area becomes an ideal location for a star ground point. a low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. the recommended pcb layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. the two input capacitors should be placed in parallel, and as close to the device supply pins as possible. the ceramic capaci - tor should be closer to the pins than the bulk capacitor. this is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. sense pins the sense resistors, rs x , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. as shown in the layout below, the sense x pins have very short traces to the rs x resistors and very thick, low impedance traces directly to the star ground underneath the device. if possible, there should be no other components on the sense circuits. note: when selecting a value for the sense resistors, be sure not to exceed the maximum voltage on the sense x pins of 500 mv. v bb cvdd1 cvdd2 ccp cvcp cin3 rs1 pad 1 A3995 cin2 cin1 rs2 mode2 out2a sense2 out2b vbb out2b sense2 out2a nc nc out1a sense1 out1b vbb out1b sense1 out1a nc phase2 vdd nc vref1 vref2 nc gnd phase1 gnd enable2 enable1 gnd cp2 cp1 vcp gnd nc mode1
dmos dual full bridge pwm motor driver A3995 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com terminal list table 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 mode2 out2a sense2 out2b vbb out2b sense2 out2a nc nc out1a sense1 out1b vbb out1b sense1 out1a nc gnd phase1 gnd nc vref2 vref1 nc vdd phase2 mode1 nc gnd vcp cp1 cp2 gnd enable1 enable2 pad pin-out diagram number name description 1 nc no connect out1a dmos full bridge 1 output a 3 sense1 sense resistor terminal for bridge 1 4 out1b dmos full bridge 1 output b 5 vbb load supply voltage 6 out1b dmos full bridge 1 output b 7 sense1 sense resistor terminal for bridge 1 8 out1a dmos full bridge 1 output a 9 nc no connect 10 phase control input 11 vdd logic supply voltage 1 nc no connect 13 vref1 analog input 14 vref analog input 15 nc no connect 16 gnd ground 17 phase1 control input 18 gnd ground 19 nc no connect 0 outa dmos full bridge output a 1 sense sense resistor terminal for bridge outb dmos full bridge output b 3 vbb load supply voltage 4 outb dmos full bridge output b 5 sense sense resistor terminal for bridge 6 outa dmos full bridge output a 7 mode control input 8 mode1 control input 9 nc no connect 30 gnd ground 31 v cp reservoir capacitor terminal 3 cp 1 charge pump capacitor terminal 33 cp charge pump capacitor terminal 34 gnd ground 35 enable1 control input 36 enable control input C pad exposed pad for enhanced thermal performance. should be soldered to the pcb
dmos dual full bridge pwm motor driver A3995 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. copyright? 2006 allegromicrosystems, inc. ev package, 36 pin qfn with exposed thermal pad 5.8 nom .228 5.8 nom .228 0.25 nom .010 32x0.20 min .008 4x0.20 min .008 0.50 nom .020 1.15 nom .045 4x0.20 min .008 4.15 nom .163 4.15 nom .163 4.15 nom .163 4.15 nom .163 0.30 0.18 .012 .007 0.05 0.00 .002 .000 6.15 5.85 .242 .230 6.15 5.85 .242 .230 0.20 ref .008 a b c seating plane c 0.08 [.003] 36x 36x 0.10 [.004] m c a b 0.05 [.002] m c 0.50 .020 1.00 0.80 .039 .031 0.75 0.35 .030 .014 36 36 2 1 2 1 36 2 1 a a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) preliminary dimensions, for reference only (reference jedec mo-220vjjd-1, except exposed thermal pad) dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown c c reference land pattern layout (reference ipc7351 qfn50p600x600x100-37v1m); adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) r0.30 ref .012 for the latest version of this document, visit our website: www.allegromicro.co m
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